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| Data Sheet, Rev. 1.0, October 2008 SPIDER - TLE7236E 8 Channel High-Side and Low-Side Relay Switch with Limp Home Mode and Cranking Automotive Power TLE7236E Table of Contents Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 2 2.1 3 3.1 3.2 4 4.1 4.2 4.3 5 5.1 5.2 5.3 5.4 6 6.1 6.2 6.3 6.4 6.5 6.6 7 7.1 7.2 7.3 7.4 7.5 7.6 8 8.1 8.2 9 9.1 9.2 9.3 9.4 9.5 9.6 10 11 12 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limp Home Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channels 4 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inductive Output Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Vbb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 11 12 13 13 13 14 15 16 16 16 17 18 19 20 21 21 21 21 21 21 22 Diagnostic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 28 29 30 31 32 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Data Sheet 2 Rev. 1.0, 2008-10-30 SPI Driver for Enhanced Relay Control TLE7236E 1 Features * * * * * * Overview 8 bit SPI for diagnostics and control, providing daisy chain capability Very wide range for digital supply voltage Two configurable input pins offer complete flexibility for PWM operation Stable behavior at under voltage Green Product (RoHS compliant) AEC Qualified PG-SSOP-24-4 Description The TLE7236E is an eight channel high-side and low-side power switch in PG-SSOP-24-4 package providing embedded protective functions. It is especially designed for standard relays and LEDs in automotive applications. The output stages incorporate two low-side, four high-side and two auto configuring high-side or low-side switches. A serial peripheral interface (SPI) is utilized for control and diagnosis of the device and the load. For direct control, there are two input pins available. The TLE7236E provides a micro controller fail-safe function which is activated via a high signal at the limp home input pin. There is a power supply integrated in the device to ensure this functionality even without digital supply voltage. The integrated power supply is designed to fulfill cranking mode requirements. The power transistors are built by N-channel power MOSFETs. The device is monolithically integrated in Smart Power Technology. Type TLE7236E Data Sheet Package PG-SSOP-24-4 3 Marking TLE7236E Rev. 1.0, 2008-10-30 TLE7236E Overview Table 1 Product Summary Operating range power supply voltage Digital supply voltage Typical On-State resistance at 25 C high-side: 2 channels (Relay) high-side: 2 channels (Generic, LED) auto configuring: 2 channels (Relay, Supplies) low-side: 2 channels (Relay) Nominal load current (all channels active) Relay LED, Generic Over load switch off threshold Output leakage current per channel at 25 C Drain to source clamping voltage Source to ground clamping voltage SPI clock frequency Protective Functions * * * Over load and short circuit protection Thermal shutdown Electrostatic discharge protection (ESD) Vbb VDD RDS(ON) 4.0 ... 28 V 3.0 ... 5.5 V 0.9 1.6 0.9 0.9 IL(nom, min) 350 mA 175 mA IDS(OVL, min) IDS(OFF, max) VDS(CL, min) Vbb(CL, max) fSCLK(max) 500 mA 1 A 41 V -16 V 5 MHz Diagnostic Functions * * * * Latched diagnostic information via SPI Open load detection in OFF-state Over load detection in ON-state Over temperature Crank Mode * Integrated power supply enables secure operation at low battery voltage Limp Home / Fail-Safe Functions * * Limp home activation via pin LHI Limp home configuration via input pins Applications * * * Especially designed for driving relays and LEDs in automotive applications All types of resistive and inductive loads Suitable to switch 5 V power supply lines by auto configuring channels Data Sheet 4 Rev. 1.0, 2008-10-30 TLE7236E Overview Detailed Description The TLE7236E is an eight channel high-side and low-side relay switch providing embedded protective functions. The output stages incorporate two low-side switches (0.9 per channel), four high-side switches (two channels with 0.9 and two channels with 1.6 ) and two auto-configuring high-side or low-side switches (0.9 per channel). The auto-configuring switches can be utilized in high-side or low-side configuration just by connecting the load accordingly. They are also suitable to switch a 5 V supply line in high-side configuration. Protective and diagnostic functions adjust automatically to the chosen configuration. The 8 bit serial peripheral interface (SPI) is utilized for control and diagnosis of the device and the loads. The SPI interface provides daisy chain capability in order to assemble multiple devices in one SPI chain by using the same number of micro-controller pins. The outstanding feature of this octal relay switch enables the output channels to keep their state at low battery voltage. This is realized by an integrated power supply, especially designed to fulfill cranking mode requirements (Vbb = 4 V) independent from digital power supply (VDD). The SPI functionality is given only when the digital power supply is available. Furthermore, the TLE7236E is equipped with two input pins that can be individually routed to the output control of each channel thus offering complete flexibility in design and PCB-layout. The input multiplexer is controlled via SPI. In limp home mode (fail-safe mode), the input pins are directly routed to the configurable output channels 4 and 5. The limp home mode operates independently of digital power supply and is activated via pin LHI. The device provides full diagnosis of the load via open load, over load and short circuit detection. SPI diagnosis flags indicate latched fault conditions that may have occurred. Each output stage is protected against short circuit. In case of over load, the affected channel switches off. There are temperature sensors available for each channel to protect the device against over temperature. The device protects itself with a build in reverse polarity protection which prohibits intrinsic current flow through the logic during reverse polarity. However the output stages still incorporate a reverse diode where current can flow through during reverse polarity. The power transistors are built by N-channel power MOSFETs. The inputs are ground referenced CMOS compatible. The device is monolithically integrated in Smart Power Technology. Data Sheet 5 Rev. 1.0, 2008-10-30 TLE7236E Block Diagram 2 Block Diagram VBB crank mode power supply temperature sensor high -side gate control LHI IN1 IN2 limp home mode activation short circuit detection control, diagnostic and protective functions open load detection input mux OUT0 OUT1 OUT2 OUT3 D4 D5 input register VDD CS SCLK SI SO SPI stand-by control auto configuring gate control S5 S4 OUT6 OUT7 low-side gate control diagnosis register reverse polarity protection GND Overview_6.emf Figure 1 Block Diagram Data Sheet 6 Rev. 1.0, 2008-10-30 TLE7236E Block Diagram 2.1 Terms Figure 2 shows all terms used in this data sheet. Vbat IS VBB IOUT_S0 OUT0 IOUT_S1 ILHI VLHI VIN1 VIN 2 VDD V CS VSCLK VSI VSO IIN1 IIN2 IDD I CS ISCLK ISI ISO SO GND IGND Terms_6.emf VDS0 VS 0 VS1 VS 2 VDS1 V DS2 VDS3 OUT1 LHI IN1 IN2 VDD CS SCLK SI OUT2 OUT3 IOUT_S2 IOUT_S3 TLE7236E D4 S4 D5 S5 OUT6 IOUT_D4 V S3 IOUT_S4 IOUT_D5 IOUT_S5 IOUT_D6 IOUT_D7 VDS4 V D4 VS 4 VDS5 VD5 VS 5 VDS6 VDS 7 OUT7 Figure 2 Terms In all tables of the electrical characteristics is valid: Channel related symbols without channel number are valid for each channel separately (e.g. VDS specification is valid for VDS0 ... VDS7). In order to make the description of output currents easier, the load current IOut is equivalent to the drain current IOUT_D in low-side configuration and the source current IOUT_S in high-side configuration. All SPI register bits are marked as follows: ADDR.PARAMETER (e.g. ICR01.INX1). In SPI register description, the values in bold letters (e.g. 0) are default values. Data Sheet 7 Rev. 1.0, 2008-10-30 TLE7236E Pin Configuration 3 3.1 l Pin Configuration Pin Assignment (top view ) n.c. n.c. OUT1 OUT3 LHI IN1 IN2 D5 OUT7 S5 n.c. n.c. 1 2 3 4 5 6 7 8 9 10 11 12 25 SUB exposed pad (bottom) 24 23 22 21 20 19 18 17 16 15 14 13 VBB OUT0 OUT2 VDD CS SCLK SI SO D4 OUT6 S4 GND PG-SSOP -24-4.emf Figure 3 Pin Configuration PG-SSOP24-4 3.2 Pin 21 24 13 25 Pin Definitions and Functions Symbol VDD VBB GND SUB I/O Function Digital power supply Power supply Digital, analog and power ground Substrate pins for thermal connection. To enable reverse polarity protection these pins must be floating Source of high side power transistor channel 0 Source of high side power transistor channel 1 Source of high side power transistor channel 2 Source of high side power transistor channel 3 Drain of auto configuring power transistor 4 Source of auto configuring power transistor 4 Drain of auto configuring power transistor 5 Source of auto configuring power transistor 5 Drain of low side power transistor channel 6 Drain of low side power transistor channel 7 Limp home activation input pin (pull down) Input multiplexer input 1 pin (pull down) Power Supply Power Stages 23 3 22 4 16 14 8 10 15 9 Inputs 5 6 LHI IN1 I I OUT0 OUT1 OUT2 OUT3 D4 S4 D5 S5 OUT6 OUT7 O O O O O O O O O O Data Sheet 8 Rev. 1.0, 2008-10-30 TLE7236E Pin Configuration Pin 7 SPI 20 19 18 17 Others 1,2,11,12 n.c. I not connected CS SCLK SI SO I I I O SPI Chip select (pull up) Serial clock Serial data in Serial data out Symbol IN2 I/O I Function Input multiplexer input 2 pin (pull down) Data Sheet 9 Rev. 1.0, 2008-10-30 TLE7236E Electrical Characteristics 4 4.1 Electrical Characteristics Absolute Maximum Ratings 1) Stresses above the ones listed here may affect device reliability or may cause permanent damage to the device. The values below are not considering combinations of different maximum conditions at one time Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Absolute Maximum Ratings1) Pos. Parameter Symbol Limit Values min. Power Supply 4.1.1 4.1.2 4.1.3 Power supply voltage Digital supply voltage Power supply voltage for full short circuit protection (single pulse) (Tj = -40 C ... 150 C) Load current channel 0, 1, 4, 5, 6, 7 channel 2, 3 4.1.5 4.1.6 4.1.7 4.1.8 Voltage at power transistor Power transistor's source voltage max. 40 5.5 28 V V V -16V max. 2 minutes - - Unit Test Conditions Vbb VDD Vbat(SC) -16 -0.3 0 Power Stages 4.1.4 IL -0.5 -0.25 - -16 - 0.5 0.25 41 - 41 A - VDS VOut_S Power transistor's drain voltage VOut_D Max. energy dissipation one channel single EAS V V V mJ - - - 2) pulse for ch. 0, 1, 4, 5, 6, 7 - - 4.1.9 Maximum energy dissipation one channel repetitive pulses for ch. 0, 1, 4, 5, 6, 7 1 * 104 cycles 1 * 106 cycles 4.1.10 Max. energy dissipation one channel single EAS pulse for ch. 2,3 - - 50 30 65 50 mJ - - 18 13 mJ Tj(0) = 105 C ID(0) = 0.35 A Tj(0) = 150 C ID(0)= 0.250 A 2) EAR Tj(0) = 105 C ID(0) = 0.250 A Tj(0) = 105 C ID(0) = 0.220 A 2) Tj(0) = 105 C ID(0) = 0.250 A Tj(0) = 150 C ID(0)= 0.250 A 1) not subject to production test Data Sheet 10 Rev. 1.0, 2008-10-30 TLE7236E Electrical Characteristics Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Absolute Maximum Ratings1) Pos. Parameter Symbol Limit Values min. 4.1.11 Maximum energy dissipation one channel repetitive pulses for ch. 2,3 1 * 104 cycles 1 * 106 cycles Logic Pins 4.1.12 Voltage at input pins 4.1.13 Voltage at LHI pin 4.1.14 Voltage at chip select pin 4.1.15 Voltage at serial clock pin 4.1.16 Voltage at serial input pin 4.1.17 Voltage at serial output pin Temperatures 4.1.18 Junction Temperature 4.1.19 Storage Temperature ESD Susceptibility 4.1.20 ESD susceptibility on all pins max. mJ - - 12 11 2) Unit Test Conditions EAR Tj(0) = 105 C ID(0) = 0.180 A Tj(0) = 105 C ID(0) = 0.180 A V V V V V V C C kV 3) VIN VLHI VCS VSCLK VSI VSO Tj Tstg VESD -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -40 -55 -2 VDD + 0.3 5.5 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 150 150 2 - 3) 3) 3) 3) - - HBM4) 1) not subject to production test 2) Pulse shape represents inductive switch off: IL(t) = IL(0) * (1 - t / tpulse); 0 < t < tpulse 3) VDD + 0.3 V < 5.5 V 4) ESD susceptibility, HBM according to EIA/JESD 22-A114 4.2 Pos. 4.2.1 4.2.2 4.2.3 Functional Range Parameter Supply Voltage Range for Nominal Operation upper Supply Voltage Range for Extended Operation lower Supply Voltage Range for Extended Operation Junction Temperature Symbol Min. Limit Values Max. 16 28 9 V V V - Parameter Deviations possible Parameter Deviations possible - 9 Unit Conditions Vbb(nom) Vbb(ext),up 16 Vbb(ext),low 4 4.2.4 Tj -40 150 C Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. Data Sheet 11 Rev. 1.0, 2008-10-30 TLE7236E Electrical Characteristics 4.3 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Thermal Resistance1) Pos. 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 Parameter Junction to Case, bottom Junction to Case, top Junction to Pin (6,7,18 or 19) Junction to Ambient (1s0p, min. footprint) Junction to Ambient (1s0p+300mm2Cu) Junction to Ambient (1s0p+600mm2Cu) Junction to Ambient (2s2p) Symbol Min. Limit Values Typ. - - - 95 50 40 31 Max. 4 35 12 - - - - K/W K/W K/W K/W K/W K/W K/W 2) 2) 2) 3) Unit Conditions RthJC,back RthJC,top RthJPin RthJA,min RthJA,300 RthJA,600 RthJA,2s2p - - - - - - - 4) 5) 6) 1) Not subject to production test 2) Specified RthJSP value is simulated at natural convection on a cold plate setup (all pins are fixed to ambient temperature). Ta = 85 C. Ch1 to Ch8 are dissipating 1 W power (0.125 W each). 3) Specified RthJA value is according to Jedec JESD51-2,-3 at natural convection on FR4 1s0p board; The product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with minimal footprint copper area and 70 m thickness. Ta = 85 C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each). 4) Specified RthJA value is according to Jedec JESD51-2,-3 at natural convection on FR4 1s0p board; The product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper area of 300mm2 and 70 m thickness. Ta = 85 C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each). 5) Specified RthJA value is according to Jedec JESD51-2,-3 at natural convection on FR4 1s0p board; The product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper area of 600mm2 and 70 m thickness. Ta = 85 C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each). 6) Specified RthJA value is according to Jedec JESD51-2,-7 at natural convection on FR4 2s2p board; The product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 m Cu, 2 x 35 m Cu). Ta = 85 C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each). Data Sheet 12 Rev. 1.0, 2008-10-30 TLE7236E Power Supply 5 Power Supply The TLE7236E is supplied by two supply voltages Vbb and VDD. The Vbb supply line is connected to a battery feed and used by the power switches and by an integrated power supply for the register banks. The internal power supply is designed to hold the state of the power switches including the configuration stored in the control register bank during cranking down to 4V. There is an under voltage reset function implemented for the Vbb power supply. After start-up of the power supply, all SPI registers are reset to their default values and the device is in sleep mode (standby). The SPI command CMD.WAKE = 1 is switching the device to operation mode (ON), while a command CMD.STB = 1 send the device to sleep mode (standby) again. The VDD supply line is used by the SPI shift register related circuitry and for driving the SO line. As a result, the daisy chain function is available as soon as VDD is provided in the specified range independent of Vbb. A capacitor between pins VDD and GND is recommended (especially in case of EMI). 5.1 Operation Modes There is a limp home functionality implemented in the TLE7236E, which is activated via pin LHI. Please refer to Section 5.2 for details. The device provides a sleep mode (stand by) to minimize current consumption, which also resets the register banks. It is entered and left by dedicated SPI commands . The sleep mode current is minimized only when limp home is inactive. After limp home, the device enters sleep mode automatically. The internal power supply is designed for low voltage cranking condition down to Vbb = 4 V. During cranking, the output channels keep their state as before configured via SPI independent of VDD supply voltage. If VDD = 0 V the SPI can not be used as the output and input levels refer to VDD, but the device keep the current state until either the limp home mode is triggered or the VDD voltages comes back and therefore the SPI Interface works again. The following table shows the operation modes depending on Vbb, VDD and the limp home input signal LHI. Operation Modes VBB VDD LHI Switches operating Limp Home SPI & daisy-chain Register Banks Diagnostic functions 0V 0V X reset 0V 5V 0V reset 0V 5V 5V reset 4V 0V 0V 4V 0V 4V reset 4V 3V 0V 12 V 0V 0V 12 V 0V 5V reset 12 V 5V 0V 12 V 5V 5V reset - 5.2 Limp Home Mode The TLE7236E offers the capability of driving dedicated channels during fail-safe operation of the system. This limp home mode is activated by a high signal at pin LHI. In limp home mode, the SPI registers are reset and the input pins are directly routed to the auto configuring channels (channel 4 and 5). As a result, the limp home operation can be chosen for high-side and low-side driven loads. Due to the integrated power supply, limp home operation is independent of digital power supply VDD. In case of stand-by, a high signal at pin LHI will wake up the device. After limp home operation, the device enters sleep mode in any case. Data Sheet 13 Rev. 1.0, 2008-10-30 TLE7236E Power Supply 5.3 Reset There are several reset trigger implemented in the device. A reset switches off all channels and sets the registers to default values. After any kind of reset, the transmission error flag (TER) is set. Under Voltage Reset: During this device condition a read on SPI always delivers the Standard Diagnostic Frame with a TER flag. This under voltage reset is released when all the supply voltages levels are above under voltage threshold. Reset Command: There is a reset command available to reset all register bits of the register bank and the diagnosis registers. As soon as CMD.RST = 1, a reset is triggered. Limp Home Mode: In limp home mode, the SPI write-registers are reset. The SPI interface is operating normally, so the limp home bit LHI as well as the diagnosis flags can be read, but no command is accepted until the device leaves the Limp home operation. Data Sheet 14 Rev. 1.0, 2008-10-30 TLE7236E Power Supply 5.4 Electrical Characteristics Unless otherwise specified: VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 C to +150 C Pos. Parameter Power Supply Vbb 5.4.1 Supply voltage for full operation 5.4.2 Supply voltage for restricted operation (no open load currents and detection ) 5.4.3 Under voltage reset threshold voltage 5.4.4 Operating current Symbol Limit Values min. typ. max. 28 9 V V 4 - Unit Test Conditions Vbb Vbb 9 - RL = 80 VDS < 1.5 V Vbb(UV) IS - - - - - - 4 15 12 V mA mA A Vbb = 16 V Vbb = 16 V all diagnosis off Vbb = 16 V VLHI = 0 V AWK= 0 1) 5.4.5 Sleep mode current with disconnected loads (stand by) IS(Sleep) - - - - - - - - - 10 13 20 5.5 3.0 0.2 Tj = 25 C1) Tj = 85 C 1) Tj = 150 C V V mA Digital Power Supply VDD 5.4.6 Logic supply voltage 5.4.7 Under voltage reset threshold voltage 5.4.8 Logic supply current VDD VDD(PO) IDD 3.0 - - fSCLK = 0 Hz VCS = 0 V AWK= 1 VCS = 0V 5.4.9 Logic supply sleep mode current IDD(Sleep) - - - - - - - - - 20 20 40 200 1 1 A VCS = VDD AWK = 0 Tj = 25 C1) Tj = 85 C 1) Tj = 150 C s s s 1) 1) 1) Timings twu(Sleep) 5.4.11 Vbb under voltage reset delay time tbb(UVR) 5.4.12 VDD under voltage reset delay time tDD(UVR) 5.4.10 Sleep mode wake-up time 1) Not subject to production test, specified by design. - - - Note: Characteristics show the deviation of parameter at the given supply voltage and junction temperature. Typical values show the typical parameters expected at Vbb = 13.5 V, VDD = 5.0 V, Tj = 25 C. Data Sheet 15 Rev. 1.0, 2008-10-30 TLE7236E Power Stages 6 Power Stages The TLE7236E is an eight channel high-side and low-side relay switch. The power stages are built by N-channel vertical power MOSFET transistors. The gates of the high-side switches are controlled by charge pumps. 6.1 Input Circuit There are two input pins available at TLE7236E, which can be configured to be used for control of the output stages. The INXn parameter of the input configuration register provide following possibilities: * * * * channel is switched off channel is switched according to signal level at input pin IN1 channel is switched according to signal level at input pin IN2 channel is switched on Figure 4 shows the input circuit of TLE7236E. IN1 IIN1 0 Channel 7 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 0 IN2 IIN2 1 INX0 InputLogic.emf Figure 4 Input Multiplexer The current sink to ground ensures that the channels switch off in case of open input pin. The zener diode protects the input circuit against ESD pulses. 6.2 Channels 4 and 5 The TLE7236E provides two auto-configuring high-side or low-side switches (channels 4 and 5). They adjust the diagnostic and protective functions according their potentials at drain and source automatically. In high-side configuration, the load is connected between ground and source of the power transistors (S4 or S5). The drain of the power transistors (D4 and D5) can be connected to any potential between GND-pin potential and VBB-pin potential. When the drain is connected to VBB, the channel behave like the other high side channels. The drain can also be connected to a 5 V power supply and the source pin will be utilized as switched 5 V supply line. In low-side configuration, the source of the power transistors are to be connected to GND. The configuration can be chosen for each of these channels individually, so it is feasible to connect one channel in low-side and the other in high-side configuration. Data Sheet 16 Rev. 1.0, 2008-10-30 TLE7236E Power Stages 6.3 Inductive Output Clamp When switching off inductive loads with low-side switches, the potential at pin OUT rises to VDS(CL) potential, because the inductance intends to continue driving the current. For the high-side channels, the potential at pin OUT drops below ground potential to VS(CL). The voltage clamping is necessary to prevent destruction of the device, see Figure 5 for details. Nevertheless, the maximum allowed load inductance is limited by the max. clamping energy EAR see electrical characteristics "EAR" on Page 10. V bb high side channel VBB low side channel OUT ID VD VDS(CL) IL L, RL V DS(CL) IS VS GND IL L, RL OUT V S(CL) GND OutputClamp.emf Figure 5 Output Clamp Implementation Maximum Load Inductance During demagnetization of inductive loads, energy has to be dissipated in the TLE7236E. This energy can be calculated with following equations: V bb - V D(CL) RL IL L E = V D(CL) ------------------------------- ln 1 - ------------------------------- + I L -----RL RL V bb - V D(CL) V S(CL) R L I L L E = ( V bb - V S(CL) ) --------------- ln 1 - --------------- + I L -----RL RL V S(CL) Low-side (1) High-side (2) These equations simplify under the assumption of RL = 0: V bb 2 1 E = -- LI L 1 - ------------------------------- 2 V bb - V D(CL) Low-side (3) V bb 2 1 E = -- LI L 1 - --------------- 2 V S(CL) High-side (4) The maximum energy, which is converted into heat, is limited by the thermal design of the component. Data Sheet 17 Rev. 1.0, 2008-10-30 TLE7236E Power Stages 6.4 Timing Diagrams The power transistors are switched on and off with a dedicated slope via the INX bits of the serial peripheral interface (SPI). The switching times tON and tOFF are designed equally. IN tON tOFF t VDS 80% 20% t SwitchOn .emf Figure 6 Switching a Resistive Load In input mode, a high signal at the input pin is equivalent to a SPI ON command and a low signal to SPI OFF command respectively. Please refer to Section 9.3 for details on SPI protocol. Data Sheet 18 Rev. 1.0, 2008-10-30 TLE7236E Power Stages 6.5 Electrical Characteristics Unless otherwise specified: VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 C to +150 C typical values: VDD = 5.0 V, VBAT = 13.5 V, Tj = 25 C Pos. Parameter Output Characteristics 6.5.1 On-State resistance channel 0, 1, 4, 5, 6, 7 Symbol Limit Values min. typ. max. - 0.9 - channel 2, 3 - 1.6 - 6.5.2 Nominal load current 2.6 - 3.9 mA 1.4 - 1.9 Unit Test Conditions RDS(ON) IOut(nom) IL = 220 mA Tj = 25 C Tj = 150 C IL = 110 mA Tj = 25 C Tj = 150 C all channels on Ta = 100 C Tj,max = 150 C based on Rthja 1) 1) channel 0, 1, 4, 5, 6, 7 channel 2, 3 6.5.3 Output leakage current in sleep mode 350 175 500 250 - - - - - - - 0.1 - 40 - - A 1 2 5 -16 - 0.6 5.5 - - 80 V V V V V A A s IOut(Sleep) - - - VDS = 13.5 V Tj = 25 C1) Tj = 85 C 1) Tj = 150 C - - - - 1) 6.5.4 Output clamping voltage Input Characteristics 6.5.5 L level of pin IN & LHI 6.5.6 H level of pin IN & LHI 6.5.7 Input voltage hysteresis at pin IN 6.5.8 L-input pull-down current through pin IN 6.5.9 H-input pull-down current through pin IN Timings 6.5.10 Turn-on time VDS = 20% Vbat channel 0, 1,4,5 channel 2, 3 channel 6,7 6.5.11 Turn-off time VDS = 80% Vbb channel 0, 1, 4, 5 channel 2, 3 (HS) channel 6, 7 (LS) 1) Not subject to production test, specified by design. VOUT_S(CL) - VOUT_DS(CL) 41 VIN(L) VIN(H) VIN 0 1.8 - 1.5 10 IIN(L) IIN(H) tON VIN = 0.6 V 1) VIN = 5 V Vbb = 13.5 V resistive load - - - - - - 100 100 100 s tOFF - - - - - - 100 100 100 IDS= 250 mA IDS= 120 mA IDS = 250 mA Vbb = 13.5 V resistive load IDS = 250 mA IDS = 120 mA IDS = 250 mA Data Sheet 19 Rev. 1.0, 2008-10-30 TLE7236E Power Stages 6.6 Command Description Input Configuration Registers ICR01 3 INX1 rw 000B 2 1 INX0 rw 0 ICR23 3 INX3 rw 001B 2 1 INX2 rw 0 ICR45 3 INX5 rw 010B 2 1 INX4 rw 0 ICR67 3 INX7 rw 011B 2 1 INX6 rw 0 Field INXn n = 7 to 0 Bits [3:2], [1:0] Type rw Description Input Multiplexer Configuration Channel n 00 Channel n is switched off 01 Channel n is switched by input 1 10 Channel n is switched by input 2 11 Channel n is switched on Data Sheet 20 Rev. 1.0, 2008-10-30 TLE7236E Protection Functions 7 Protection Functions The device provides embedded protective functions. Integrated protection functions are designed to prevent IC destruction under fault conditions described in this data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation. 7.1 Over Load Protection The TLE7236E is protected in case of over load or short circuit of the load. After time tOFF(OVL), the over loaded channel n switches off and the according diagnosis flag Dn is set. The channel can be switched on after clearing the protection latch by command CMD.CPL = 1. The CPL command clears itself with the next valid SPI communication frame. Please refer to Figure 7 for details. IN t ID0 I D0(OV L) tOFF(OV L) CPL = 1 b D0 = 00 b t OverLoad.emf D0 = 1b Figure 7 Shut Down at Over Load 7.2 Over Temperature Protection A temperature sensor for each channel causes an overheated channel to switch off to prevent destruction. The according diagnosis flag is set. This flag is also set in OFF state, if the regarding channel temperature is too high.The channel can be only switched on after clearing the protection latch by SPI command CMD.CPL = 1. The CPL command clears itself with the next valid SPI communication frame. Please refer to "Diagnostic Features" on Page 23 for information on diagnosis features. 7.3 ESD protection There is a designed in protection against ESD disturbances up to the specified limit by using the defined model. Please see electrical characteristics "ESD susceptibility on all pins" on Page 11 7.4 Reverse Polarity Protection There is a reverse polarity protection implemented in the TLE7236E. This protection has to be divided into two parts. First the protection of the control circuits and second in the protection of the power transistors. The control circuits are reverse polarity protected by protective measures in the ground connection. In case of reverse polarity, there is no current flow through the control circuits. The digital pins need serial resistors if the connected input stages are not floating to ground. The power transistors contain intrinsic body diodes that cause power dissipation. The reverse current through these intrinsic body diodes has to be limited by the connected loads. The over temperature and over load protection are not active during reverse polarity. 7.5 Loss of Vbb In case of loss of Vbb connection in on-state, all inductances of the loads have to be demagnetized through the ground connection or through an additional path from Vbb to ground. Then for example, a diode (see D2 in Figure 14 "Application Diagram" on Page 35) can be placed. Data Sheet 21 Rev. 1.0, 2008-10-30 TLE7236E Protection Functions 7.6 Electrical Characteristics Unless otherwise specified: VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 C to +150 C typical values: VDD = 5.0 V, VBAT = 13.5 V, Tj = 25 C Pos. Parameter Over Load Protection 7.6.1 Over load detection current at channel 0,1,4,5,6,7 7.6.3 Over load shut-down delay time Over Temperature Protection 7.6.4 Thermal shut down temperature 1) Not subject to production test, specified by design Symbol min. Limit Values typ. max. 1.0 0.5 60 150 1701) Unit Test Conditions IOut(OVL) 0.5 0.22 A A s C 7.6.2 Over load detection current at channel 2,3 IOut(OVL) tOFF(OVL) Tj(SC) Data Sheet 22 Rev. 1.0, 2008-10-30 TLE7236E Diagnostic Features 8 Diagnostic Features The SPI of TLE7236E provides diagnosis information about the device and about the load. The diagnosis information of the protective functions of channel n is latched in the diagnosis flags Dn. It is cleared by the SPI command CMD.CPL = 1. The CPL command clears itself with the next valid SPI communication frame. The open load diagnosis of channel n is latched in the diagnosis flag OLn. This flag is cleared by reading the according diagnosis register. Following table shows possible failure modes and the according protective and diagnostic action. Failure Mode Open Load Comment Diagnosis, when channel n is switched on: none Diagnosis, when channel n is switched off: according to voltage level at the output pin, flag OLn is set after time td(OL). A diagnosis current can be enabled by SPI command DCCR.DCENn = 1. When over temperature occurs, the according diagnosis flag Dn is set. If the affected channel n was active it is switched off. The diagnosis flags are latched until they have been cleared by SPI command CMD.CPL = 1. When over load is detected at channel n, the affected channel is switched off after time tOFF(OVL) and the dedicated diagnosis flag Dn is set. The diagnosis flags are latched until they have been cleared by SPI command CMD.CPL = 1. Over Temperature Over Load (Short Circuit) Data Sheet 23 Rev. 1.0, 2008-10-30 TLE7236E Diagnostic Features 8.1 Electrical Characteristics Unless otherwise specified: VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 C to +150 C typical values: VBAT = 13.5 V, VDD = 5.0 V, Tj = 25 C Pos. Parameter Symbol Limit Values min. OFF State Diagnosis 8.1.1 8.1.2 8.1.3 Open load diagnosis delay time typ. - - - Uni Test Conditions t max. s V A - 1) td(OL) 100 250 3.9 300 High Side Channels 0,1,2,3 Open load detection threshold voltage for VD(OL0..3) 2.3 Channel 0,1,2,3 Output diagnosis current channel 0,1,2,3 IL(DC0..3) 50 measured at VD(OL) threshold 1) Configurable Channels 4,5 8.1.4 8.1.5 8.1.6 Open load detection threshold voltage for VD(OL4,5) 1 Channel 4,5 in all configurations Output diagnosis current channel 4,5 in high side configuration Output diagnosis current channel 4,5 in low side configuration - - - 2.2 300 100 V A A IL(DCHS) IL(DCLS) 80 20 measured at VD(OL) threshold measured at VD(OL) threshold 1) Low side Channels 6,7 8.1.7 8.1.8 Open load detection threshold voltage for VD(OL6,7) Channel 6,7 Output diagnosis current channel 6,7 - 50 - 2.2 100 V A IL(DC6,7) measured at VOL threshold - - - ON State Diagnosis (see also Protection in Chapter 7) 8.1.9 Over load detection current at channel 0,1,4,5,6,7 IL(OVL) IL(OVL) 0.5 0.22 - - - 1.0 0.5 60 A A s 8.1.10 Over load detection current at channel 2,3 8.1.11 Over load detection delay time at channel tOFF(OVL) - 0,1,4,5,6,7 1) Open load detection voltages are referenced to ground Data Sheet 24 Rev. 1.0, 2008-10-30 TLE7236E Diagnostic Features 8.2 Command Description Diagnosis Registers (read only, register bank RB = 1) DR01 3 OL1 r 2 D1 r 00B 1 OL0 r 0 D0 r DR23 3 OL3 r 2 D3 r 01B 1 OL2 r 0 D2 r DR45 3 OL5 r 2 D5 r 10B 1 OL4 r 0 D4 r DR67 3 OL7 r 2 D7 r 11B 1 OL6 r 0 D6 r Field Dn n = 7 to 0 OLn n = 7 to 0 Bits 2, 0 Type r Description Diagnostic Feedback of Channel n 0 normal operation 1 over load or over temperature switch off occurred Open Load Detection of Channel n 0 normal operation 1 Open load at OFF-state occurred 3, 1 r r/ CMD Command Register 3 Wake r/w 2 STB r/w 110B 1 RST r/w 0 CPL r/w Field CPL RST STB Wake Data Sheet Bits 0 1 2 3 Type r/w r/w r/w r/w Description please refer to Section 7 for description please refer to Section 5.3 for description please refer to Section 5 for description please refer to Section 5 for description 25 Rev. 1.0, 2008-10-30 TLE7236E Diagnostic Features Diagnosis Current Configuration Register DCCR0 3 DCEN3 r/w 2 DCEN2 r/w 100B 1 DCEN1 r/w 0 DCEN0 r/w DCCR1 3 DCEN7 r/w 2 DCEN6 r/w 101B 1 DCEN5 r/w 0 DCEN5 r/w Field DCENn n = 7 to 0 Bits 3 to 0 Type r/w Description Diagnosis Current Enable Channel n 0 Diagnosis current disabled 1 Diagnosis current enabled Data Sheet 26 Rev. 1.0, 2008-10-30 TLE7236E Serial Peripheral Interface (SPI) 9 Serial Peripheral Interface (SPI) The diagnosis and control interface is based on a serial peripheral interface (SPI). The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability. SO SI CS SCLK time CS MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB SPI.emf Figure 8 Serial Peripheral Interface The SPI protocol is described in Section 9.3. It is reset to the default values after reset. 9.1 SPI Signal Description CS - Chip Select: The system micro controller selects the TLE7236E by means of the CS pin. Whenever the pin is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. CS High to Low transition: * * The diagnosis information is transferred into the shift register. SO changes from high impedance state to high or low state depending on the logic OR combination between the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration, a high signal indicates a faulty transmission. For details, please refer to Figure 9. This information stays available to the first rising edge of SCLK. TER SI OR 1 0 SO SI CS SCLK S SPI SO S TER.emf Figure 9 Transmission Error Flag on SO Line Data Sheet 27 Rev. 1.0, 2008-10-30 TLE7236E Serial Peripheral Interface (SPI) CS Low to High transition: * Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, ...) of eight SCLK signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the command is ignored. Data from shift register is transferred into the input matrix register. * SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any transition. SI - Serial Input: Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read on the falling edge of SCLK. The 8 bit input data consist of two parts (control and data). Please refer to Section 9.3 for further information. SO Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 9.3 for further information. 9.2 Daisy Chain Capability The SPI of TLE7236E provides daisy chain capability. In this configuration several devices are activated by the same CS signal MCS. The SI line of one device is connected with the SO line of another device (see Figure 10), which builds a chain. The ends of the chain are connected with the output and input of the master device, MO and MI respectively. The master device provides the master clock MCLK, which is connected to the SCLK line of each device in the chain. device 1 MO SI SPI SO SI device 2 SPI SO SI device 3 SPI SO CS CS SCLK SCLK CS MI MCS MCLK Figure 10 Daisy Chain Configuration In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The bit shifted out can be seen at SO. After 8 SCLK cycles, the data transfer for one device has been finished. In single chip configuration, the CS line must go high to make the device accept the transferred data. In daisy chain configuration the data shifted out at device #1 has been shifted in to device #2. When using three devices in daisy chain, three times 8 bits have to be shifted through the devices. After that, the MCS line must go high (see Figure 11). Data Sheet 28 SCLK SPI_DasyChain.emf Rev. 1.0, 2008-10-30 TLE7236E Serial Peripheral Interface (SPI) MI MO MCS MCLK time SO device 3 SI device 3 SO device 2 SI device 2 SO device 1 SI device 1 SPI_DasyChain2.emf Figure 11 Data Transfer in Daisy Chain Configuration 9.3 SPI Protocol The control and diagnosis function of the TLE7236E is based on two register banks which are accessed via following SPI protocol. The control register bank contains eight registers (with 4 bit each) addressed by a 3 bit pointer. The diagnosis register bank contains four registers (with 4 bit each) addressed by a 2 bit pointer. An additional indication bit is available to differentiate between standard diagnosis information and data read from a register bank. Control and Diagnosis Mode CS1) SI SI SI S O S O S O TER 7 1 6 5 ADDR ADDR 4 3 2 DATA 1 0 Write Register Command Read Register Command 0 Read Standard Diagnosis 0 Standard Diagnosis 0 0 AWK LH D67 D45 D23 D01 x x x x x 1 x x x 0 RB Second Frame of Read Command TER TER 0 1 1 ADDR (Diagnosis) ADDR (Control) DATA DATA 1) This bit is valid between CS hi -> lo and first SCLK lo -> hi transition. Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame, the output at SPI signal SO will contain the requested information. Any command can be executed in the second frame. Data Sheet 29 Rev. 1.0, 2008-10-30 TLE7236E Serial Peripheral Interface (SPI) Field TER Bits Type Description Transmission Error 0 Previous transmission was successful (modulo 8 clocks received) 1 Previous transmission failed or first transmission after reset RB 0 Register Bank 0 CONTR Control Register Bank 1 DIAG Diagnosis Register Bank (read only) Address Pointer to register for read and write command Data Data written to or read from register selected by address ADDR ADDR DATA 6:4 3:0 Standard Diagnosis: Field AWK LH Dxy Bits 5 4 3, 2, 1, 0 Type Description Awake, Device active Limp home mode active Failure mode alert of channel x and y 9.4 Register Overview Control Register Bank Name ICR01 ICR23 ICR45 ICR67 DCCR0 DCCR1 CMD unused Addr 000B 001B 010B 011B 100B 101B 110B 111B DCEN3 DCEN7 WAKE - 3 INX1 INX3 INX5 INX7 DCEN2 DCEN6 STB - DCEN1 DCEN5 RST - 2 1 INX0 INX2 INX4 INX6 DCEN0 DCEN4 CPL - 2) 0 default1) 0H 0H 0H 0H 0H 0H 0H 0H type r/w r/w r/w r/w r/w r/w w - 1) The default values are set after Vbb power-on, STB-command and RST-command All command bits are cleared at the end of transmission, respectively after execution 2) CPL bit needs a valid next SPI communication frame to be cleared Data Sheet 30 Rev. 1.0, 2008-10-30 TLE7236E Serial Peripheral Interface (SPI) Diagnosis Register Bank (read only) Name DR01 DR23 DR45 DR67 Addr 000B 001B 010B 011B 3 OL1 OL3 OL5 OL7 2 D1 D3 D5 D7 1 OL0 OL2 OL4 OL6 0 D0 D2 D4 D6 9.5 Timing Diagrams tCS(lead) tCS(lag) tSCLK(P) tSCLK(H) tSCLK(L) 0.7Vcc 0.2Vcc tCS(td) 0.7Vcc 0.2Vcc CS SCLK tSI(su) tSI(h) SI tSO(en) tSO(v) tSO(dis) 0.7Vcc 0.2Vcc SO 0.7Vcc 0.2Vcc SPI Timing.emf Figure 12 Timing Diagram Data Sheet 31 Rev. 1.0, 2008-10-30 TLE7236E Serial Peripheral Interface (SPI) 9.6 Electrical Characteristics Unless otherwise specified: VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 C to +150 C typical values: VDD = 5.0 V, VBAT = 13.5 V, Tj = 25 C Pos. Parameter Input Characteristics (CS, SCLK, SI) 9.6.1 L level of pin CS SCLK SI 9.6.2 H level of pin CS SCLK SI 9.6.3 L-input pull-up current through CS 9.6.4 H-input pull-up current through CS 0 - Symbol min. Limit Values typ. max. 0.2*VDD V - Unit Test Conditions VCS(L) VSCLK(L) VSI(L) VCS(H) VSCLK(H) VSI(H) ICS(L) ICS(H) 0.5*VDD - VDD V - 5 2.5 40 - 90 - A A VCS = 0 V VDD = 5 V 1) VDD = 5 V VCS = 0.5*VDD 1) 9.6.5 L-input pull-down current through pin ISCLK(L) SCLK ISI(L) SI 9.6.6 H-input pull-down current through pin ISCLK(H) SCLK ISI(H) SI Output Characteristics (SO) 9.6.7 L level output voltage 9.6.8 H level output voltage 9.6.9 Output tristate leakage current Timings 9.6.10 Serial clock frequency 9.6.11 9.6.12 9.6.13 9.6.14 1.5 - - A VDD = 5 V VSCLK = VSI = 0.2*VDD 1) A 10 40 80 VDD= 5 V VSCLK = VSI = VDD ISO = +2 mA ISO = -1.5 mA VCS = VDD VSO(L) VSO(H) ISO(OFF) 0 - - - - - - - - - - - - 0.4 V VDD 0.4 V -10 0 200 50 50 250 250 250 20 20 VDD 10 5 - - - - - - - - A fSCLK Serial clock period tSCLK(P) Serial clock high time tSCLK(H) Serial clock low time tSCLK(L) Enable lead time (falling CS to rising tCS(lead) SCLK) MHz - ns ns ns ns ns ns ns ns - 1) 1) 1) 9.6.15 Enable lag time (falling SCLK to rising tCS(lag) CS ) 9.6.16 Transfer delay time (rising CS to falling CS ) 9.6.17 Data setup time (required time SI to falling SCLK) 9.6.18 Data hold time (falling SCLK to SI) 1) tCS(td) tSI(su) tSI(h) 1) 1) 1) Data Sheet 32 Rev. 1.0, 2008-10-30 TLE7236E Serial Peripheral Interface (SPI) Unless otherwise specified: VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 C to +150 C typical values: VDD = 5.0 V, VBAT = 13.5 V, Tj = 25 C Pos. Parameter Symbol min. 9.6.19 Output enable time (falling CS to SO tSO(en) valid) 9.6.20 Output disable time (rising CS to SO tSO(dis) tri-state) 9.6.21 Output data valid time with capacitive tSO(v) load 1) Not subject to production test, specified by design. Limit Values typ. - - - max. 200 200 100 - - - Unit Test Conditions ns ns ns CL = 20 pF 1) CL = 20 pF 1) CL = 20 pF 1) Data Sheet 33 Rev. 1.0, 2008-10-30 TLE7236E Package Outlines 10 Package Outlines Stand Off (1.47) 1.7 MAX. 0.35 x 45 2x 0.1 C D 3.9 0.11) 0.19 +0.06 0.64 0.25 0.1+0 -0.1 0.65 0.25 0.05 2) 0.2 M C C A-B D 24x 0.08 C Seating Plane D 6 0.2 8 MAX. M 0.2 D A 24 13 Bottom View 1 12 24 13 B 8.65 0.1 Index Marking 0.1 C A-B 2x 6.4 0.25 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.13 max. PG-SSOP-24-4-PO V01 Figure 13 PG-SSOP-24-4 (Plastic Green Slim Small Outline Package) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pbfree finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Data Sheet 34 Dimensions in mm Rev. 1.0, 2008-10-30 2.65 0.25 1 12 TLE7236E Application Information 11 Application Information Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Figure 14 shows a simplified application circuit. Vdd need to be externally reverse polarity protected. D1 Vbat C1 Lowside Loads C2 VDD VDD VBB OUT0 OUT1 OUT2 D2 PWM PWM LHO IN1 IN2 LHI OUT3 D3 D4 S4 D5 S5 CS SCLK SPI uC SI SO OUT6 OUT7 GND Highside Loads Application _LG.emf Figure 14 Application Diagram Note: This is a very simplified example of an application circuit. The function must be verified in the real application. The circuit above shows a example of using this device in a automotive target application. D1,C1 are used for blocking negative disturbances from Battery supply. D2 is optional for loss of battery if no other circuit on this battery feed can limit the voltage to the negative max. rating of the device (-16 V) . D3 is limiting the battery voltage below the maximum rated positive voltage of the VBB pin (40 V). C2 is for EMC and to stabilize the digital driver, recommended value is 47nF. There are no resistors to the C needed due to the internal reverse polarity protection. For further information you may contact http://www.infineon.com/ Data Sheet 35 Rev. 1.0, 2008-10-30 TLE7236E Revision History 12 Revision Rev. 1.0 Revision History Date 2008-10-30 Changes released Datasheet Data Sheet 36 Rev. 1.0, 2008-10-30 Edition 2008-10-30 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. |
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